1. Field of the Invention
The present invention relates to a semiconductor memory device which combines a volatile semiconductor storage with a nonvolatile semiconductor storage.
2. Description of the Prior Art
A conventional semiconductor memory device of the type referred to above is constructed in such a manner as shown in, for example, FIG. 3. Specifically, the semiconductor memory device of FIG. 3 has a nonvolatile semiconductor storage, a control unit and a volatile semiconductor storage formed on a P-type semiconductor substrate 21. The nonvolatile semiconductor storage is provided with a transistor M2 comprised of a drain area located at one end of an n-type impurity diffusion layer 22, a floating gate 25 and a control gate 27. A control unit is provided so as to switch the storing mode, and it includes a switching transistor M3 which has control gate 27 in common with transistor M2, and which is provided with an n-type source area 30. Further, the volatile semiconductor storage is provided with a word line selection transistor Ml which is comprised of an n-type drain area 29, a word line selection control gate 28 and a source area located at the other end of the above n-type impurity diffusion layer 22, and a capacitor C having a capacitor gate 35 formed at the central portion of the n-type impurity diffusion layer 22 via a SiO.sub.2 film 34. In the above construction, for switching the storing mode, a predetermined voltage is applied to control gate 27 or to capacitor gate 35, so that the data stored in capacitor C of the volatile semiconductor storage is transferred to transistor M2 of the nonvolatile semiconductor memory unit.
As is described hereinabove, however, capacitor C of the conventional semiconductor memory device is constructed in such a manner that capacitor gate electrode 35 is confrontingly provided on the surface at the central part of the n-type impurity diffusion layer 22. Therefore the n-type impurity diffusion layer 22 is consequently increased in size or area, causing an increase of the size of the memory cell.